Module-based Synthesis of Behavioral Verilog Descriptions to Asynchronous Circuits

In this paper we present a design tool for automatic synthesis of Verilog behavioral description of an asynchronous circuit into delay insensitive presynthesized library modules, using syntax directed techniques. Our design tool can also generate appropriate output to support implementing the circuit on ASICs and LUT-based FPGAs consequently rapid prototyping of the asynchronous circuit becomes readily available using the proposed tool. General Terms Design, Languages